Code Style Release Procedures
Building Building EXTRAS
Develop Branch v19.0.0.0 v20.0.0.0 v20.0.0.2 v20.0.0.3 v20.1.0.0 v20.1.0.1 v20.1.0.5 v21.0.0.0 v21.0.1.0 v21.1.0.0 v21.1.0.1 v21.1.0.2
Creating Disk Images Devices m5term Building Linux ARM Kernel Building Android Marshmallow Guest binaries
Memory System gem5 Memory System Replacement Policies Indexing Policies Classic memory system coherence Classic caches
Ruby Cache Coherence Protocols Garnet 2.0 MOESI CMP directory Garnet Synthetic Traffic SLICC MI example Garnet standalone Interconnection network MOESI hammer MOESI CMP token MESI two level CHI Replacement Policies
SimpleCPU O3CPU TraceCPU Minor CPU Model Execution Basics Visualization
GCN3
Garnet Synthetic Traffic Ruby Random Tester
Trace-based Debugging Debugger-based Debugging Debugging Simulated Code Reporting Problems
Edit this page

ARM Implementation

Supported features and modes

The ARM Architecture models within gem5 support an ARMv8.0-A profile of the ARM® architecture with multi-processor extensions. This includes both AArch32 and AArch64 state at all ELs. This basically means supporting:

The baseline model is ARMv8.0 compliant, we also support some mandatory/optional ARMv8.x features (with x > 0) While the best way to get a synced version of Arm architectural features is to have a look at Arm ID registers:

Here you will find a summary of some (but not all) notable`architectural extensions supported in gem5: